The present invention relates to a manufacturing technology of a semiconductor device, and more specifically, to a technology effectively applied to lead-free exterior solder plating in a semiconductor device having a small die pad structure.
In a typical assembly process of manufacturing a semiconductor package equipped with a semiconductor chip (semiconductor device), die bonding, wire bonding, resin sealing and the like are carried out one after another. Thereafter, in an exterior plating process, a tin (Sn)-lead (Pb) based solder layer is typically formed as an exterior plating on a surface spot including a contact portion (surface to be packaged) of a substrate of a lead (hereinafter referred to as an outer lead) that is not sealed with molding resin in order to be packaged onto a printed circuit board or a circuit board.
However, in recent years, countermeasures against environmental damage have become very important, especially with regard to lead (Pb). For example, as pointed out in Japanese Patent Laid-Open No. 5-270860, it is required to reduce lead to an appropriate level, even in electronic parts such as a semiconductor devices, a packaging boards and the like, from an environmental viewpoint. Therefore, it is preferable to provide solders which replace tin (Sn)-lead (Pb) based solder, and such a proposal has been made in, for example, in Japanese Patent Laid-Open Applications No. 10-93004, No. 11-179586, No. 11-221694, No. 11-330340 and the like.
First, in Japanese Patent Laid-Open No. 10-93004, an invention using tin (Sn)-bismuth (Bi) based solder as lead-free solder to replace tin-lead based solder has been proposed. In particular, a technology for making solder connections easier has been described by forming a tin-bismuth based alloy layer on an external connection electrode lead wire of electronic parts.
Further, in Japanese Patent Laid-Open No. 11-179586, a technology for ensuring sufficient connection strength by use of Sn—Ag—Bi based solder has been proposed as a lead-free solder which replaces tin-lead based solder.
Additionally, in Japanese Patent Laid-Open No. 11-221694, a technology for improving reliability of a connection portion by use of Sn—Ag—Bi—In based solder has been proposed as a lead-free solder which replaces tin-lead based solder.
Also, in Japanese Patent Laid-Open No. 11-330340, a semiconductor device in which an Sn—Bi based plating film is formed on a lead has been introduced, and a technology for preventing the occurrence of cracks and being capable of a solder connection with a high degree of reliability has been proposed.
In the case where Sn—Pb eutectic substitutional lead-free solder is employed in exterior plating, an Sn base alloy is typically selected depending on the applications. Especially in applications such as car packaging parts, presently developing mobile electronic equipment and highly reliable parts, an alloy that is excellent in bonding strength and in heat resistant fatigue characteristics is desired. As an Sn base alloy that is excellent in bonding strength and in heat resistant fatigue characteristics, and which also has high reliability, an Sn—Ag based alloy is known. The fusion point of Sn—Pb eutectic solder is generally 183° C. while the fusion point of most Sn—Ag based alloys is 200° C. or more. Therefore, the temperature is higher for the fusion point of Sn—Ag based alloys than the fusion point of the Sn—Pb eutectic solder.
Therefore, at present, the reflow temperature for packaging a semiconductor integrated circuit using Sn—Pb eutectic substitutional lead-free solder inevitably becomes high. Therefore, the present inventors have packaged a semiconductor integrated circuit device in which an inner lead is Ag plated and an outer lead is plated at a reflow temperature higher than the conventional reflow temperature by use of lead-free substitutional solder whose the fusion point is higher than that of Sn—Pb eutectic solder, and have conducted evaluations thereof. As a result, it has been found that product failures are caused due to wire disconnection.
As a countermeasure for such wire disconnection, the present applicant has considered that hard palladium (pd) plating could be performed on a wire joining portion of an inner lead and thereby the thickness of a bonding root portion of a wire is ensured to increase the bonding strength, as shown in Japanese Patent Application No. 2000-46724. However, there is a problem that the palladium plating increases the cost.
Note that, in the above-mentioned four references, there are no descriptions that, in the case of using lead-free solder, the reflow temperature becomes high and thereby the reflow margin of the semiconductor device becomes small. There is also no description regarding countermeasures for this problem.
An object of the present invention is to provide a semiconductor device and a method of manufacturing the semiconductor device, which improves a reflow characteristic and realizes a practical lead-free arrangement.
Another object of the present invention is to provide a semiconductor device and a method of manufacturing the semiconductor device, which suppresses increases in cost in lead-free arrangements.
The above-mentioned and other objects and novel features of the present invention will become apparent from the present description in conjunction with the appended drawings.